how to create a makefile for c program from commandline

Without target name: make With target name: make all Output: gcc is compiler name, main.c, misc.c source file names, -o is linker flag and main is binary file name.Ĭommand make is used to compile program through Makefile, since there are only one target all in the Makefile, so we do not need to mention target name because first target is got compiled automatically.all is a target name, insert : after target name.Insert comment followed by # character.Here we will declare and define a function named myFunc() to print something – this function will be defined and declared in misc.c and misc.h respectively. Suppose, we have 3 files main.c (main source file), misc.c (source file that contains function definition), misc.h (that contain function declaration). You can compile your project (program) any number of times by using Makefile. In a single make file we can create multiple targets to compile and to remove object, binary files. Makefile is a set of commands (similar to terminal commands) with variable names and targets to create object file and to remove them.

Makefile is a tool to simplify or to organize code for compilation. To solve such kind of problem, we use Makefile because during the compilation of large project we need to write numbers of source files as well as linker flags are required, that are not so easy to write again and again. If you have multiple source files in c, c++ and others language and want to compile them from Terminal Command, it is hard to write every time. What is Makefile for C program compilation and How to create Makefile? Makefile in Linux for Compilation

How to create a makefile for c program from commandline